NES:Hardware information

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Revision as of 17:06, 7 September 2016 by Tepples (talk | contribs) (Galaxian (J only) is 128 Kbit. Kirby's Adventure is 6 Mbit. Metal Slader Glory (J only) is 8 Mbit. And "UNROM with register set to 0" isn't the only power-up state of the mapper.)
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The Nintendo Entertainment System (NES for short) consists of:

  • 2A03 Central Processing Unit
    • A 6502 8-bit (using a custom MOS Technology 6502 class) Processor running at 1.789Mhz
    • On-die PSG sound supporting 5 channels:
      • 2 pulse wave
      • 1 triangle wave
      • 1 noise
      • 1 DPCM
    • 16 Kbit (2kb) of RAM
  • 2C02 Picture Processing Unit
    • 16 Kbit (2kb) of VRAM
    • Screen Resolution of 256x240
    • 52 Colors Available (four levels of gray, and four levels of each of 12 hues)
    • 8 color emphasis modes
    • Up to 25 colors on screen through normal means, though with special tricks, several hundred colors can be on screen
    • Maximum of 64 sprites
    • Maximum of 8 sprites per scanline
    • 8x8 or 8x16 sprite size
    • Two picture scrolls, Horizontal and Vertical
  • Game Pak
    • Min/Max attested cart size: 192 Kbit - 6 Mbit (Famicom: 128 Kbit - 8 Mbit)
    • More than 320 Kbit requires bank switching hardware
    • Some games contain extra RAM for the CPU and/or PPU

ROM Layout

In iNES format, a cartridge ROM consists of a 16-byte header, followed by the cartridge's dedicated program data banks ("PRG ROM") ordered from first to last, followed by the dedicated video graphics banks ("CHR ROM") also so sequenced. The header is not stored as such in the cartridge; it is instead a machine-readable description of the bank switching hardware, extra RAM, and other hardware on the game's circuit board.

Example of a 96k rom with 4 PRG banks and 4 CHR banks:

$00000 Header
$00010 PRG Bank 1
$04010 PRG Bank 2
$08010 PRG Bank 3
$0C010 PRG Bank 4
$10010 CHR Bank 1
$12010 CHR Bank 2
$14010 CHR Bank 3
$16010 CHR Bank 4
$18010 End of file


On Startup

On startup, the NES begins program execution by reading a 16-bit address from address $FFFC in memory and jumping there, as if the instruction JMP ($FFFC) were executed. The banks switched in at startup depend on which mapper is in use. Often, the last 16k of ROM is fixed in $C000-$FFFF, and the bank in $8000-$BFFF is random. Another common situation is that a random 32k bank is loaded into $8000-$FFFF; the reset vector in each bank then needs to point to valid code in that bank.

See Also